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71514hk no.a2279-1/30 http://onsemi.com semiconductor components industries, llc, 2014 july, 2014 ver. 1.04 ordering information see detailed ordering and shipping informa tion on page 30 of this data sheet. lc87f2l08a overview the lc87f2l08a is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8k-byte flash rom (on-board-programmable), 256-byte ram, an on-chip-debugger, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), an asynchronous/synchronous sio interface, a 12/8-bit 9-channel ad converter, four analog comparator, two amp circuits, an igbt control circuit(pp g), a watch dog timer, an internal reset a system clock frequency divider, and a 19-source 10-vector interrupt feature. features ? flash rom ? 8192 ? 8 bits ? capable of on-board programming with a power voltage range of 4.5 to 5.5v ? block-erasable in 128 byte units ? writing in 2-byte units ? rom ? 256 ? 9 bits ? package : dip30sd(400mil), lead-free type ? minimum bus cycle time ? 83.3ns (12mhz) note : the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time ? 250ns (12mhz) cmos lsi 8-bit microcontroller 8k-byte flash rom / 256-byte ram / 30-pin ordering number : en*a2279 * this product is licensed from silicon storage technology, inc. (usa). advance information this document contains information on a new product. specifications and information herein are subject to change without notice. dip30sd(400mil)
lc87f2l08a no.a2279-2/30 ? ports normal withstand voltage i/o ports ports i/o direction can be designated in 1 bit units 9(p14, p15, p20, p21, p30, p70 to p73) ports i/o direction can be designated in 4 bit units 8 (p0n) dedicated ppg ports 7 (ppgo, amp1i, amp2o, cmp1ia, cmp1ib, cmp2i, cmp4i) dedicated oscillator ports/input ports 2 (cf1/xt1, cf2/xt2) reset pin 1 (res#) power pins 3 (vss1, vss2, vdd1) ? timers timer 0 : 16-bit timer/counter with a capture register. mode 0 : 8-bit timer with an 8-bit programma ble prescaler (with an 8-bit capture register) ? 2 channels mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3 : 16-bit counter (with a 16-bit capture register) timer 1 : 16-bit timer/counter mode 0 : 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler mode 2 : 16-bit timer/counter with an 8-bit prescaler mode 3 : 16-bit timer with an 8-bit prescaler timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) base timer 1) the clock is selectable from the subclock (32.768 khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts are programmable in 5 different time schemes ? high-speed clock counter can count clocks with a maximum clock rate of 20 mhz (at a main clock of 10 mhz). ? sio sio1 : 8-bit asynchronous/synchronous serial interface mode 0 : synchronous 8-bit serial i/o (2-wire configuration, 2 to 512 tcyc transfer clocks) mode 2 : bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3 : bus mode 2 (start detect, 8 data bits, stop detect) ? uart full duplex 7/8/9 bit data bits selectable 1 stop bit (2-bit in continuous data transmission) built-in baudrate generator ? ad converter : 12 bits/8 bits ? 9 channels 12 /8 bits ad converter resolution selectable ? remote control receiver circuit (shari ng pins with p73, int3, and t0in) noise rejection function (noise filter time constant selectable from 1tcyc/32tcyc/128tcyc) ? clock output function can generate clock outputs with a frequency of 1 1 , 2 1 , 4 1 , 8 1 , 16 1 , 32 1 , 64 1 of the source clock selected as the system clock. can generate the source clock for the subclock.
lc87f2l08a no.a2279-3/30 ? analog comparator ? 4 channels cmp1 : both input terminals of ?+? and ?-?. output: for timing generation of ppg output and capture timer input(int2). cmp2 : input terminal of ?+?, ?-? input is 2/3vdd of internal vref. interrupt flag set of output (int0). cmp 3: ?+? input is output of amp1. ?- ? input is 2/3vdd of internal vref. ppg output control of cmp3 output (off only at a present cycle) and interrupt flag set (int1). cmp4 : input terminal of ?+?, ?-? input is 2/3vdd of internal vref. ppg output control of cmp4 output (compulsion off) and interrupt flag set(cmp4). ? amp circuit ? 2 channels amp1 : the magnification is set by the user option ( ? 6/ ? 8/ ? 10). input terminal (amp1i) output is cmp3 input and amp2 input. amp2 : the magnification is set by the register ( ? 1/ ? 2/ ? 4). input is amp1 output. output rerminal (amp2o) ? pulse output control circuit (ppg output) ? 1 channels output synchronous signal switch : set by the register (1 pulse output) / continuous pulse output of synchronizationto cmp1 output . duty control : the pulse beginning delay time and the pulse end time form synchronous idle are set according to the register. ppg output is compulsion off by the cmp3/cmp4 output. cmp1 output : timing detection of pulse signal. the output polarity can be switched : user option setting. ? watchdog timer can generate the internal reset signal on a timer overflow monitored by the wdt-dedicated low-speed rc oscillation clock (30khz). allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/ hold mode. setting at pulse end time setting at pulse beginning delay time
lc87f2l08a no.a2279-4/30 ? interrupts 19 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highes t (x)) of multiplex interrupt c ontrol. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l uart1 receive 8 0003bh h or l sio1/uart1 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/cmp4 priority levels x > h > l of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 128levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions 16 bits ? 8 bits (5 tcyc execution time) 24 bits ? 16 bits (12 tcyc execution time) 16 bits 8 bits (8 tcyc execution time) 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits internal oscillation circuits low-speed rc oscillation circuit 1 : for system clock(100khz) medium-speed rc oscillation circuit : for system clock(1mhz) multifrequency rc oscillation circuit : for system clock(8mhz) low-speed rc oscillation circuit 2 : for watch dog timer(30khz) external oscillation circuits hi-speed cf oscillation circuit : for system clock, with internal rf low speed crystal oscillation circuit : for lo w-speed system clock, with internal rf 1) the cf and crystal oscillation circuits share the same pi ns. the active circuit is selected under program control. 2) both the cf and crystal oscillator circuits stop operation on a system reset. when the reset is released, only the cf oscillation circuit resumes operation. ? system clock divider function can run on low current. the minimum instruction cycle selectable from 300 ns, 600 ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10 mhz).
lc87f2l08a no.a2279-5/30 ? internal reset function power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 8 le vels (1.67v, 1.97v, 2.07v, 2.37v, 2.57v, 2.87v, 3.86v, and 4.35v) through option configuration. low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level (7 levels: 1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v, 4.28v). ? standby function halt mode: halts instruction execution while allowi ng the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer or low-voltage detection (3) occurrence of an interrupt hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) system resetting by watchdog timer or low-voltage detection (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0. x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circuits except the base timer. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) system resetting by watchdog timer or low-voltage detection. (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0. (5) having an interrupt source established in the base timer circuit. note: available only when x?tal oscillation is selected.
lc87f2l08a no.a2279-6/30 ? on-chip debugger supports software debugging with the ic mounted on the target board. ? data security function (flash versions only) protects the program data stored in flash memory from unauthorized read or copy. note : this data security function does not necessarily provide absolute data security. ? development tools on-chip-debugger : tcb87 typeb + lc87f2l08a ? programming board package programming board dip30sd w87f2ld ? flash rom programmer maker model supported version device flash support group, inc. (fsg) single programmer af9708 af9709/af9709b/af9709c (including ando electric co., ltd. models) rev03.12 lc87f2l08a gang programmer af9723/af9723b(main body) (including ando electric co., ltd. models) *1 lc87f2l08a af9833(unit) (including ando electric co., ltd. models) *1 on semiconductor single/gang programmer skk/skk type b (sanyofws) application version 1.04 or later chip data version 2.18 or later lc87f2l08 gang programmer skk-4g (sanyofws) in-circuit/gang programmer skk-dbg type b (sanyofws) note : check for the latest version. *1 : we have a schedule to request the registration. for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp
lc87f2l08a no.a2279-7/30 package dimensions unit : mm pdip30 / dip30sd (400 mil) case 646az issue a xxxxxxxxxx ymddd xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking.
lc87f2l08a no.a2279-8/30 pin assignment dip30sd ?lead-free type? dip30sd name dip30sd name 1 p30/int5//t1in/buz/cmp1o 16 cmp4i 2 ppgo 17 amp2o 3 res# 18 vss2 4 vss1 19 p04/an4 5 cf1/xt1 20 p05/an5/cko/dbgp00 6 cf2/xt2 21 p06/an6/t6o/dbgp01 7 vdd1 22 p07/t7o/dbgp02 8 amp1i 23 p70/int0/t0lcp/an8 9 cmp1ia 24 p71/int1/t0hcp/an9 10 cmp1ib 25 p72/int2/t0in 11 cmp2i 26 p73/int3//t0in 12 p00/an0 27 p20/utx/int4/t1in 13 p01/an1 28 p21/urx/int4/t1in 14 p02/an2 29 p14/sb1 15 p03/an3 30 p15/sck1 p15/sck1 p14/sb1 p21/urx/int4/t1in p20/utx/int4/t1in p73/int3//t0in p72/int2/t0in p71/int1/t0hcp/an9 p70/int0/t0lcp/an8 p07/t7o/dbgp02 p06/an6/t6o/dbgp01 p05/an5/cko/dbgp00 p04/an4 vss2 amp2o cmp4i p30/int5//t1in/buz/cmp1o ppgo res# vss1 cf1/xt1 cf2/xt2 vdd1 amp1i cmp1ia cmp1ib cmp2i p00/an0 p01/an1 p02/an2 p03/an3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
lc87f2l08a no.a2279-9/30 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 ppg sio1 timer 0 timer 1 port 3 port 7 adc alu flash rom pc acc b register c register psw rar ram stack pointer port 2 int4 base timer timer 6 int0-2 int3 (noise filter) timer 7 on-chip-debugger clock generator cf/ x ' tal rc mrc port 2 reset control reset circuit (lvd/por) wdt(src2) res# uart1 port 3 int5 src1
lc87f2l08a no.a2279-10/30 pin function chart pin name i/o description option vss1 vss2 ? ? power supply pins no vdd1 ? ?? power supply pin no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 4 bit units ? pull-up resistors can be turned on and off in 4 bit units. ? hold reset input ? port 0 interrupt input ? pin functions p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output p00(an0) to p06(an6):ad converter input p05(dbgp00) to p07(dbgp02):on-chip debugger port yes p00 to p07 port 1 i/o ? 2-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p14: sio1 data i/o p15: sio1 clock i/o yes p14 to p15 port 2 i/o ? 2-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p20 : uart transmit p21 : uart receive p20 to p21 : int4 input / hold reset input / timer 1 event input / timer 0l capture input / timer 0h capture input interrupt acknowledge type yes p20 to p21 rising falling rising & falling h level l level int4 ? ? ? ? ? ? 1-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p30: buz output/cmp1o output/ int5 input/hold reset input / timer 1 event input / timer 0l capture input/ti mer 0h capture input interrupt acknowledge type yes p30 rising falling rising & falling h level l level int5 ? ? ? ? ?
lc87f2l08a no.a2279-11/30 pin name i/o description option port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p70 : int0 input / hold reset input / timer 0l capture input p71 : int1 input / hold reset input / timer 0h capture input p72 : int2 input / hold reset input / timer 0 event input / timer 0l capture input p73 : int3 input (with noise filter) / timer 0 event input / timer 0h capture input p70(an8),p71(an9) : ad converter input interrupt acknowledge type no p70 to p73 rising falling rising & falling h level l level int0 int1 int2 int3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? amp1i i amp1 input no amp2o o amp2 output no cmp1ia i cmp1 input(-) no cmp1ib i cmp1 input(+) no cmp2i i cmp2 input(+) no cmp4i i cmp4 input(+) no ppgo o ppg output yes res i/o external reset input / internal reset output no cf1/xt1 i ? ceramic resonator or 32.768khz crystal oscillator input pin ? pin function general-purpose input port no cf2/xt2 i/o ? ceramic resonator or 32.768khz crystal oscillator output pin ? pin function general-purpose input port no
lc87f2l08a no.a2279-12/30 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable (note 1) 2 nch-open drain no p14 to p15 p20 to p21 p30 1 bit 1 cmos programmable 2 nch-open drain programmable p30 to p31 1 bit 1 cmos programmable 2 nch-open drain programmable p70 ? no nch-open drain programmable p71 to p73 ?? no cmos programmable ppgo ?? 1 cmos no 2 nch-open drain no note 1 : the control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low- and high-impedance pull- up connection is exercised in nibble (4-bit) units (p00 to 03 or p04 to 07). user option table option name option to be applied on flash-rom version option selected in units of option selection port output type p00 to p07 ? 1 bit cmos nch-open drain p14 to p15 ? 1 bit cmos nch-open drain p20 to p21 ? 1 bit cmos nch-open drain p30 ? 1 bit cmos nch-open drain ppgo ? - cmos nch-open drain ppgo output polarity ppgo ? - not inverted inverted magnification of amp1 - ? - x6 x8 x10 program start address - ? - 00000h 01e00h low-voltage detection reset function detect function ? - enable : use disable : not used detect level ? - 7-level power-on reset function power-on reset level ? - 8-level
lc87f2l08a no.a2279-13/30 recommended unused pin connections pin name recommended unused pin connections board software p00 to p07 open output low p14 to p15 open output low p20 to p21 open output low p30 open output low p70 to p73 open output low cf1/xt1 pulled low with a 100k ? resistor or less general-purpose input port cf2/xt2 pulled low with a 100k ? resistor or less general-purpose input port on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled "rd87 onchip debugger installation manual" and "lc872000 series onchip debugger pin connection requirements" note : be sure to electrically short-circuit between the vss1 and vss2 pins.
lc87f2l08a no.a2279-14/30 1. absolute maximum ratings at ta=25 ? c, v ss 1= v ss 2= 0v parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit maximum supply voltage vddmax vdd1 ? ? +6.5 v input voltage vi cf1, res#, amp1i, cmp1ia,cmp1ib, cmp2i, cmp4i ? ? vdd+0.3 output voltage vo amp2o, ppgo ? ?? vdd+0.3 input/output voltage vio cf2, ports 0, 1, 2, 3, port 7 ? ? vdd+0.3 high level output current peak output current ioph(1) ports 0, 1, 2, 3, ppgo cmos output select per 1 applicable pin ? ? 5 mean output current (note 1-1) iomh(1) ports 0, 1, 2, 3, ppgo cmos output select per 1 applicable pin ? ? 3 total output current ioah(1) p71 to p73 total of all applicable pins ? ioah(2) ports 0, 1, 2, 3, ppgo total of all applicable pins ? ioal(1) p00 to p03 total of all applicable pins 40 ioal(2) p04 to p07, ports 1, 2, 3, 7, ppgo total of all applicable pins 40 ioal(3) ports 0, 1, 2, 3, 7, ppgo total of all applicable pins 70 power dissipation pdmax(1) dip30sd ta= ? ? c package only 350 mw pdmax(2) ta= ? ? c package with thermal resistance board (note 1-2) 540 operating ambient temperature topr ? ? +85 ? c storage ambient temperature ts t g ? ? +125 note 1-1 : the mean output current is a mean value measured over 100ms. note 1-2 : semi standards therma l resistance board (size : 76.1114 .31.6tmm, glass epoxy) is used. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
lc87f2l08a no.a2279-15/30 2. allowable operating conditions at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd [ v ] min. t y p. max. unit operating supply voltage (note 2-1) vdd vdd1 0.245s ? ? ? ? system clock frequency division ratio = 1/1 ? external system clock duty = 50 ? 5% 4.5 to 5.5 0.1 12 mhz ? ? system clock frequency division ratio = 1/2 ? external system clock duty = 50 ? 5% 4.5 to 5.5 0.2 24.4 oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 12 mhz ceramic oscillation see fig. 1. 4.5 to 5.5 12 mhz fmcf(2) cf1, cf2 10 mhz ceramic oscillation see fig. 1. 4.5 to 5.5 10 fmcf(3) cf1, cf2 4 mhz ceramic oscillation. cf oscillation normal amplifier size selected. see fig. 1. (cflamp=0) 4.5 to 5.5 4 4 mhz ceramic oscillation. cf oscillation low amplifier size selected. (cflamp=1) see fig. 1. 4.5 to 5.5 4 fmmrc frequency variable rc oscillation. 1/2 frequency division ratio. (rcctd=0) (note 2-4) 4.5 to 5.5 7.44 8.0 8.56 fmrc internal medium-speed rc oscillation 4.5 to 5.5 0.5 1.0 2.0 fmsrc1 internal low-speed rc oscillation 1 4.5 to 5.5 50 100 200 khz fmsrc2 internal low-speed rc oscillation 2 4.5 to 5.5 15 30 60 fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 4.5 to 5.5 32.768 note 2-1 : v dd must be held greater than or equal to 2.2 v in the flash rom onboard programming mode. note 2-2 : relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3 : see tables 1 and 2 for the oscillation constants. note 2-4 : when switching the system clock, allow an oscillation stabilization time of 100 s or longer after the multifrequency rc oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc87f2l08a no.a2279-16/30 3. electrical characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification vdd[v] min. typ. max. unit high level input current iih(1) ports 0, 1, 2, 3 ports 7, cmp1ia, cmp1ib, cmp2i, cmp4i, amp1i, res# output disabled pull-up resistor off vin=vdd (including output tr's off leakage current) 4.5 to 5.5 1 a iih(2) cf1 vin=vdd 4.5 to 5.5 15 low level input current iil(1) ports 0, 1, 2, 3 ports 7, cmp1ia, cmp1ib, cmp2i, cmp4i, amp1i, res# output disabled pull-up resistor off vin=vss (including output tr's off leakage current) 4.5 to 5.5 ? ? ? ? ? 1 v voh(4) port 3,ppgo ioh= ? ? 1 low level output voltage vol(1) ports 0, 1, 2, 3, ppgo iol=10ma 4.5 to 5.5 1.5 vol(2) iol=1.4ma 4.5 to 5.5 0.4 vol(4) port 7 iol=1.4ma 4.5 to 5.5 0.4 vol(6) p00, p01 iol=25ma 4.5 to 5.5 1.5 vol(7) iol=4ma 4.5 to 5.5 0.4 pull-up resistance rpu(1) ports 0, 1, 2, 3 port 7 voh=0.9vdd when port 0 selected low-impedance pull-up. 4.5 to 5.5 18 50 230 k ? ? c 4.5 to 5.5 10 pf note 3-1 : 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.050.10.150.20.250.30.35 amp2o (v) output sink current (ma) o o u t p u t c h a r a c t e r i s t i c s c u r r e n t s i n k i n g 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -5 -4 -3 -2 -1 0 amp2o (v) output source current (ma) o u t p u t c h a r a c t e r i s t i c s c u r r e n t s o u r c i n g product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc87f2l08a no.a2279-17/30 4. serial i/o characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v 4-1. sio1 serial i/o characteristics (note 4-1-1) parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit serial clock input clock frequency tsck(3) sck1(p15) ? ? ? see fig. 5. 4.5 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14) ? ? see fig. 5. 4.5 to 5.5 0.05 s data hold time thdi(2) 0.05 serial output output delay time tdd0(4) sb1(p14) ? ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 5. 4.5 to 5.5 (1/3)tcyc +0.08 note 4-1-1 : these specifications are theoretical values. add margin depending on its use. 5. pulse input conditions at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p21), int5(p30 to p31) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 4.5 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 256 tpil(5) res# ? resetting is enabled. 4.5 to 5.5 200 s
lc87f2l08a no.a2279-18/30 6. ad converter characteristics at v ss 1= v ss 2=0v <12bits ad converter mode / ta= ? 40 to +85 ? c > parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit resolution n an0(p00) to an6(p06) an8(p70) an9(p71) 4.5 to 5.5 12 bit absolute accuracy et (note 6-1) 4.5 to 5.5 ? 16 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.5 to 5.5 32 115 s analog input voltage range vain 4.5 to 5.5 vss vdd v analog port input current iainh vain=vdd 4.5 to 5.5 1 a iainl vain=vss 4.5 to 5.5 ? <8bits ad converter mode / ta= ? 40 to +85 ? c > parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit resolution n an0(p00) to an6(p06) an8(p70) an9(p71) 4.5 to 5.5 8 bit absolute accuracy et (note 6-1) 4.5 to 5.5 ? 1.5 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.5 to 5.5 20 90 s analog input voltage range vain 4.5 to 5.5 vss vdd v analog port input current iainh vain=vdd 4.5 to 5.5 1 a iainl vain=vss 4.5 to 5.5 ? conversion time calculation formulas : 12bits ad converter mode : tcad(conversion time)=((52/(ad division ratio))+2)(1/3)tcyc 8bits ad converter mode : tcad(conversion time)=((32/(ad division ratio))+2)(1/3)tcyc external oscillation (fmcf) operating supply voltage range (vdd) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) ad conversion time (tcad) 12bit ad 8bit ad cf-12mhz 4.5v to 5.5v 1/1 250ns 1/8 34.8s 21.5s cf-10mhz 4.5v to 5.5v 1/1 300ns 1/8 41.8s 25.8s cf-4mhz 4.5v to 5.5v 1/1 750ns 1/8 104.5s 64.5s note 6-1 : the quantization error (1/2l sb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2 : the conversion time refers to the period from th e time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: the first ad conversion is performed in the 12-b it ad conversion mode after a system reset. the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
lc87f2l08a no.a2279-19/30 7. power-on reset (por) characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification option selected voltage min. typ. max. unit por release voltage porrl ? select from option. (note 7-1) 1.67v 1.55 1.67 1.79 v 1.97v 1.85 1.97 2.09 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 7. (note 7-2) 0.7 0.95 power supply rise time poris ? power supply rise time from 0v to 1.6v. 100 ms note7-1 : the por release level can be selected out of 8 levels only when the lvd reset function is disabled. note7-2 : por is in an unknown state before transistors start operation. 8. low voltage detection r eset (lvd) characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification option selected voltage min. typ. max. unit lvd reset voltage (note 8-2) lvdet ? select from option. (note 8-1) (note 8-3) ? see fig. 8. 1.91v 1.81 1.91 2.01 v 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 4.28v 4.18 4.28 4.38 lvd hysteresis width lvhys 1.91v 55 mv 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 4.28v 65 detection voltage unknown state lvuks ? see fig. 8. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw ? lvdet-0.5v ? see fig. 9. 0.2 ms note8-1 : the lvd reset level can be selected out of 7 levels only when the lvd reset function is enabled. note8-2 : lvd reset voltage specification values do not include hysteresis voltage. note8-3 : lvd reset voltage may exceed its specification valu es when port output state changes and/or when a large current flows through port. note8-4 : lvd is in an unknown state before transistors start operation.
lc87f2l08a no.a2279-20/30 9. amplifier and comparator characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit input common-mode voltage (note9-1) vcmin cmp1ia, cmp1ib, cmp2i,cmp4i 4.5 to 5.5 vss vdd ? 1.5v v internal reference voltage vref ?-? inputs of cmp2, cmp3, cmp4 4.5 to 5.5 2/3vdd ? 0.02 2/3vdd 2/3vdd +0.02 amp input voltage (note9-2) vamin amp1i 4.5 to 5.5 vss (vdd ? 1.5v) / magnific ation of amp v offset voltage voff(1) cmp1ia, cmp1ib (cmp1) input common-mode voltage range 4.5 to 5.5 ? 20 mv voff(2) cmp2i (cmp2), cmp4i (cmp4) ? ? including vref error 4.5 to 5.5 ? 40 voff(3) amp1i (cmp3) ? ? magnification of amp1 is selected x8 by user option ? including vref error 4.5 to 5.5 ? 28 amp output error vaer amp2o ? ? magnification of amp1 is selected x8 by user option ? magnification of amp2 is selected x1 by resister 4.5 to 5.5 ? 155 ? 200 mv cmp1 response speed tc1rt cmp1o(p30) ? ? input amplitude=100mv ? over drive=50mv 4.5 to 5.5 200 ns cmp3 response speed (note9-3) tc3rt ppgo ? ? amp1i rising timing ? amp1i=(vref100mv)/8 ? see fig. 10. 4.5 to 5.5 600 cmp4 response speed tc4rt ppgo ? ? cmp4i=vref50mv ? see fig. 10. 4.5 to 5.5 200 note9-1 : when v dd =5v, the comparison input voltage is effective from 0 to 3.5v. note9-2 : magnification of amp= magnific ation of amp1 magnification of amp2 when v dd =5v, magnification of amp1 to ? 8 magnification of amp2 to ? 1, the amp input voltage is effective from 0 to 0.4375v. note9-3 : ppgo have a delay of 1/6tcyc to 1/2tcyc from cmp1o falling timing for synchronization with system clock, when the pulse start delay setup register (address: fe92h, fe93h) is set to 000h.
lc87f2l08a no.a2279-21/30 10. consumption current characteristics at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd [ v ] min. t y p. max. unit normal mode consumption current (note 10-1) (note 10-2) iddop(1) vdd1 ? fmcf=12 mhz ceramic oscillation mode ? system clock set to 12 mhz sid e ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 8.7 16 ma iddop(2) ? fmcf=4 mhz ceramic oscillation mode ? system clock set to 4 mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 4.4 8.7 iddop(3) ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4 mhz ceramic oscillation mode ? system clock set to 4 mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 4.5 to 5.5 2.6 4.8 iddop(4) ? fsx?tal=32.768 khz crystal oscillation mode ? internal low speed rc oscillation stopped. ? system clock set to internal medium speed rc oscillation. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 4.5 to 5.5 2.1 3.8 iddop(5) ? fsx?tal=32.768 khz crystal oscillation mode ? internal low speed and medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 4.5 to 5.5 6.7 11.3 iddop(6) ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 1.6 2.6 iddop(7) ? fsx?tal=32.768 khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 4.5 to 5.5 1.6 2.6
lc87f2l08a no.a2279-22/30 parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit halt mode consumption current (note 10-1) (note 10-2) iddhalt(1) vdd1 ? halt mode ? fmcf=12 mhz ceramic oscillation mode ? system clock set to 12 mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 4.4 8.7 ma iddhalt(2) ? halt mode ? fmcf=4 mhz ceramic oscillation mode ? system clock set to 4 mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 2.9 5.5 iddhalt(3) ? halt mode ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4 mhz ceramic oscillation mode ? system clock set to 4 mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 4.5 to 5.5 2.2 3.9 iddhalt(4) ? halt mode ? fsx?tal=32.768 khz crystal oscillation mode ? internal low speed rc oscillatio n stopped. ? system clock set to internal medium speed rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 4.5 to 5.5 1.9 3.1 iddhalt(5) ? halt mode ? fsx?tal=32.768 khz crystal oscillation mode ? internal low speed and medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 4.5 to 5.5 3.3 5.9 iddhalt(6) ? halt mode ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 4.5 to 5.5 1.5 2.5 iddhalt(7) ? halt mode ? fsx?tal=32.768 khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 4.5 to 5.5 1.6 2.6
lc87f2l08a no.a2279-23/30 parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit hold mode consumption current (note 10-1) (note 10-2) (note 10-3) iddhold vdd1 hold mode ? fsx?tal=32.768 khz crystal oscillation mode ? lvd option selected 4.5 to 5.5 1.5 2.6 ma note10-1 : values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note10-2 : the consumption current values do not includ e operational current of lvd function if not specified. note10-3 : amp/cmp circuit is operating in hold mode.
lc87f2l08a no.a2279-24/30 11. f-rom programming characteristics at ta=+10 to +55 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit onboard programming current iddfw(1) vdd1 ? only current of the flash block. 4.5 to 5.5 5 10 ma programming time tfw(1) ? erasing time 4.5 to 5.5 20 30 ms tfw(2) ? programming time 40 60 s 12. uart (full duplex) operating conditions at ta= ? 40 to +85 ? c, v ss 1= v ss 2=0v parameter symbol pin/remarks conditions specification v dd[v] min. typ. max. unit transfer rate ubr utx(p20) urx(p21) 4.5 to 5.5 16/3 8192/3 tcyc data length : 7/8/9 bits (lsb first) stop bits : 1 bit(2-bit in continuous data transmission) parity bits : none example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit data recepti on mode processing (first receive data=55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit ubr receive data (lsb first) start of reception end of reception stop bit start bit
lc87f2l08a no.a2279-25/30 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a on semiconductor-designated oscillation characteristic s evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1. characteristics of a sample main system clock oscillator circuit with a ceramic oscillator cf oscillation normal amplifier size selected (cflamp=0) ? murata nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 12mhz smd cstce12m0g52-r0 (10) (10) open 680 4.5 to 5.5 0.1 0.5 internal c1,c2 10mhz smd cstce10m0g52-r0 (10) (10) open 680 4.5 to 5.5 0.1 0.5 lead cstls10m0g53-b0 (15) (15) open 680 4.5 to 5.5 0.1 0.5 8mhz smd cstce8m00g52-r0 (10) (10) open 1k 4.5 to 5.5 0.1 0.5 lead cstls8m00g53-b0 (15) (15) open 1k 4.5 to 5.5 0.1 0.5 6mhz smd cstcr6m00g53-r0 (15) (15) open 1.5k 4.5 to 5.5 0.1 0.5 lead cstls6m00g53-b0 (15) (15) open 1.5k 4.5 to 5.5 0.1 0.5 4mhz smd cstcr4m00g53-r0 (15) (15) open 1.5k 4.5 to 5.5 0.2 0.6 lead cstls4m00g53-b0 (15) (15) open 1.5k 4.5 to 5.5 0.2 0.6 cf oscillation low amplifier size selected (cflamp=1) ? murata nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 4mhz smd cstcr4m00g53-r0 (15) (15) open 1k 4.5 to 5.5 0.2 0.6 internal c1,c2 cstcr4m00g53095-r0 (15) (15) open 1k 4.5 to 5.5 0.2 0.6 lead cstls4m00g53-b0 (15) (15) open 1k 4.5 to 5.5 0.2 0.6 cstls4m00g53095-b0 (15) (15) open 1k 4.5 to 5.5 0.2 0.6 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 3).
lc87f2l08a no.a2279-26/30 characteristics of a sample s ubsystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a on semiconductor-designated oscillation characteristic s evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2. characteristics of a sa mple subsystem clock oscillator ci rcuit with a crystal oscillator ? epson toyocom nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [s] max [s] 32.768khz smd mc-306 8pf 8pf open 0 ? 4.5 to 5.5 1.00s 1.50s applicable cl value = 7.0pf the oscillation stabilization time refers to the time interval that is required for the oscilla tion to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 3). note : the components that are involved in os cillation should be pl aced as close to the ic and to one another as possible becau se they are vulnerable to the influences of the circuit pattern. figure 1. cf and xt oscillator circuit figure 2. ac timing measurement point 0.5vdd cf2/xt2 cf1/xt c1 rd c cf/x?tal rf
lc87f2l08a no.a2279-27/30 figure 3. oscillation stabilization times power supply res# internal medium speed rc oscillation cf1 , cf2 operating mode reset time un p redictable reset instruction execution reset time and oscillation stabilization time internal medium speed rc oscillation or low speed rc oscillation cf1, cf2 (note) state hold reset signal hold reset signal absent tmscf/tmsxtal hold halt vdd operating vdd lower limit 0v hold reset signal and oscillation stabilization time tmscf/tmsxtal note : external oscillati on circuit is selected. hold reset signal valid
lc87f2l08a no.a2279-28/30 note : external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information. figure 4. reset circuit figure 5. serial i/o output waveforms figure 6. pulse input timing signal waveform c res vdd r res res# tpil tpih di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 siocl k : datain : dataout : dataout : datain : siocl k : tsc k tsckl tsckh thdi tsdi tddo
lc87f2l08a no.a2279-29/30 figure 7. waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only when pow er is turned on starting at the vss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the vss level as shown in (a). if such a case is an ticipated, use the lvd functi on together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the vss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 8. waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent th e repetitions of reset release and entry cycles near the detection level. v dd res# por release voltage (porrl) unknown-state (pouks) (a) (b) reset period reset period 100 s or longer v dd res# lvd hysteresis width (lvhys) unknown-state (lvuks) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet)
lc87f2l08a ps no.a2279-30/30 figure 9. low voltage detection minimum width (example of momentary power loss / voltage variation waveform) figure 10. cmp response time ordering information device package shipping (qty / packing) LC87F2L08AU-DIP-E dip30sd(400mil) (pb-free) 20 / fan-fold v dd lvd reset voltage t lvdw v ss lvd release volta g e lvdet-0.5v vref+50mv vref vref ? 50mv (vref+100mv)/8 vref/8 (vref ? 100mv)/8 amp1i cmp4i ppgo tc3rt tc4rt on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner.

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